Multi-core processors present significant challenges to designers due to tradeoffs between performance, power consumption, and thermal constraints. In general, cooling and packaging technology do not scale with device technology and therefore limit the power consumption of a multi-core processor. Thermal issues are especially relevant in heterogeneous system architecture (HSA) devices that use processors capable of executing multiple instructions in parallel. For example, traditional VLIW processors try to schedule as many instructions as possible to achieve instruction level parallelism (ILP) by fetching and packing multiple instructions into large instruction words that are dispatched and executed on multiple functional units in parallel. When all of the functional units of a processor core are used, the increased power consumption of the functional units can cause excessive chip temperature that violates thermal constraints and may ultimately damage or destroy the device. In some cases, device packaging or cooling mechanisms may be employed to address this problem, but obviously add to the cost, size and complexity of the device.
Problems associated with thermal constraints, such as chip overheating, increased power consumption, and decreased performance are especially problematic for mobile devices that have tight power and packaging constraints. New processing techniques, such as computational sprinting were developed to solve some of these problems, but under certain conditions may add stress during operation. Most multicore processors are at least partially idle for periods of time and then potentially entirely active for certain other periods of time as needs dictate. Computational sprinting is a technique that dynamically activates otherwise powered-down cores for short bursts of intense activity in response to conditions such as sporadic user activity. During this active time, the cores operate in parallel and the processor generates heat at a rate that can far exceed the thermal and electrical capacities of the device. Thus, sprinting is typically performed by running the processor until a thermal threshold is reached, at which time a controller then shuts down most of the cores and runs only one or a less number of cores to keep the temperature down. FIG. 1 illustrates the operation of a dynamic sprinting technique according to known methods. As shown in FIG. 1, an example processor 100 comprises eight individual functional units 104 denoted FU1-FU8. Processor 100 illustrates an example VLIW architecture that can pack up to eight instructions 102 (denoted Instruction1 to Instruction8) together and execute them simultaneously by eight functional units 104 in one processor cycle. Each functional unit 104 executes a respective instruction 102 so that at a particular time, all of the functional units are executing their respective instructions simultaneously. When the thermal threshold is reached, a lesser number of functional units (in the illustrated example all but one functional unit (e.g., FU1) is shut-down. As shown in FIG. 1, control transition 106 causes FU2-FU8 to stop executing and FU1 to continue executing instruction 1. The functional unit shut-down 106 occurs when the system senses that the thermal constraints of the device have been exceeded, at which time a defined number of cores or functional units are then simply deactivated until an acceptable thermal condition is reached. This is a run-time solution in that it occurs as the chip is executing instructions in real time, and requires an on-chip thermal sensor to provide the thermal condition signals to the controller. It is also a coarse-granularity solution in that it operates at the core-level, and shuts down a processor core (or other functional unit) completely, and leaves only one or a few cores operating per clock cycle. This present approach imposes certain hardware overhead and, while relatively effective in preventing failure due to thermal overload, it does not fully provide constant performance benefits in that cores that were activated to increase throughput are abruptly shutdown for indeterminate periods of time.
The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches.